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? e96y05b81 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 1300 mw operating conditions supply voltage 9?.5 v description the CXA2069Q is a 7-input, 3-output audio/video switch featuring i 2 c bus compatibility for tvs. this ic has input pins that are compatible with s2 protocol. features 4 inputs that are compatible with s2 protocol serial control with i 2 c bus 7 inputs, 3 outputs the desired inputs can be selected independently for each of the 3 outputs wide band video amplifier (20 mhz, ? db) y/c mix circuit slave address can be changed (90h/92h) audio muting from external pin high impedance maintained by i 2 c bus lines (sda, scl) even when power is off wide audio dynamic range (3 vrms typ.) applications audio/video switch featuring i 2 c bus compatibility for tvs structure bipolar silicon monolithic ic s2-compatible 7-input 3-output audio/video switch 64 pin qfp (plastic) CXA2069Q
2 CXA2069Q block diagram t v v 1 v 2 v 3 v 4 v 5 v 6 8 1 5 3 0 2 2 6 0 6 3 1 5 3 6 d b 6 d b 6 d b 6 d b 6 d b 6 d b 6 d b 6 d b 6 d b 3 1 0 1 7 2 4 y 1 y 2 y 3 y 4 5 1 2 1 9 2 6 c 1 c 2 c 3 c 4 3 9 3 7 4 9 4 7 4 6 4 4 4 1 5 8 5 6 5 5 5 1 v o u t 1 y i n 1 y o u t 1 t r a p 1 c o u t 1 c i n 1 v / y o u t 2 t r a p 2 c o u t 2 v o u t 3 y o u t 3 c o u t 3 b i a s 5 7 5 0 v g n d b i a s 2 9 1 6 2 9 2 3 5 9 6 2 6 d b 0 d b 6 d b 0 d b 6 d b 6 d b 4 1 1 1 8 3 1 2 5 6 1 6 4 6 d b 6 d b 3 5 4 2 5 2 5 4 4 0 3 8 4 5 4 3 v c c a g n d l o u t 1 r o u t 1 l o u t 2 r o u t 2 l o u t 3 r o u t 3 l o g i c 6 7 2 0 1 4 1 3 2 8 2 7 2 1 3 6 3 4 3 3 3 2 4 8 d c o u t s c l s d a a d r s - 1 s - 2 s - 3 s - 4 s 2 - 1 s 2 - 2 s 2 - 3 s 2 - 4 m u t e l t v l v 1 l v 2 l v 3 l v 4 l v 5 l v 6 r t v r v 1 r v 2 r v 3 r v 4 r v 5 r v 6 a u d i o s y s t e m i s a t t e n u a t e d b y 6 d b a t i n p u t , a n d a t o t a l g a i n i s 0 d b ( l o u t 1 a n d r o u t 1 c a n b e c h a n g e d t o 6 d b ) .
3 CXA2069Q pin configuration 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 4 2 3 1 5 a d r r v 5 v 5 l v 5 s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 6 v 6 r v 6 l t v t v r t v c x a 2 0 6 9 q 2 1 2 2 2 3 2 4 2 0 2 6 2 7 2 8 2 9 2 5 3 0 3 1 3 2 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 6 3 6 2 6 1 6 0 6 4 5 8 5 7 5 6 5 5 5 9 5 4 5 3 5 2 v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 s 2 - 2 c i n 1 b i a s y i n 1 m u t e c o u t 2 t r a p 2 r o u t 2 l o u t 2 v c c v o u t 3 r o u t 3 y o u t 3 l o u t 3 c o u t 3 d c o u t a g n d s d a s c l v / y o u t 2
4 CXA2069Q pin description pin symbol pin equivalent circuit description no. voltage 63 1 8 15 22 30 60 3 10 17 24 49 5 12 19 26 51 62, 2 9, 16 23, 29 59, 64 4, 11 18, 25 31, 61 53 41 tv v1 v2 v3 v4 v5 v6 y1 y2 y3 y4 yin1 c1 c2 c3 c4 cin1 ltv, lv1 lv2, lv3 lv4, lv5 lv6, rtv rv1, rv2 rv3, rv4 rv5, rv6 vout1 vout3 4.0 v 4.0 v 4.5 v 4.5 v 3.9 v v c c 8 6 0 1 3 0 2 2 6 3 1 5 0 1 5 3 a v c c 2 4 1 7 1 0 1 5 0 3 a 4 9 3 v c c 2 6 1 9 1 2 1 5 0 5 1 5 2 7 k 2 0 k v c c 2 5 1 8 1 1 3 1 4 1 5 k 3 3 k 6 1 6 4 2 3 1 6 9 2 9 2 5 9 6 2 2 7 k v c c v c c 5 3 4 1 2 7 k 2 3 . 5 k 3 0 k 2 5 0 video signal inputs. input composite video signals. y/c separation signal inputs. input luminance signals. the yin1 pin inputs the signal obtained by y/c separating the vout1 pin output. y/c separation signal inputs. input chrominance signals. the cin1 pin inputs the signal obtained by y/c separating the vout1 pin output. audio signal inputs. video signal outputs. output composite video signals.
5 CXA2069Q pin symbol pin equivalent circuit description no. voltage 44 56 39 58 47 37 52 43 38 54 45 40 6 13 20 27 v/yout2 yout1 yout3 cout1 cout2 cout3 lout1 lout2 lout3 rout1 rout2 rout3 s2-1 s2-2 s2-3 s2-4 3.8 v 3.3 v 3.8 v 4.5 v 4.5v 4 4 v c c v c c v c c v c c v c c v c c v c c v c c 3 9 5 6 v c c v c c v c c v c c 3 7 5 8 4 7 v c c v c c 4 0 3 8 4 5 4 3 5 2 5 4 5 6 2 0 k 2 0 k v c c v c c v c c 6 2 0 1 3 2 7 1 4 7 1 0 0 k video signal output. either composite video signal output or luminance signal output can be selected by i 2 c bus control. video signal outputs. output luminance signals. video signal outputs. output chrominance signals. audio signal outputs. zo=50 (within dc 2 ma) detects the s2-compatible dc superimposed onto the c signal. 4 : 3 video signal at 1.3 v or less 4 : 3 letter-box signal at 1.3 v or more to 2.5 v or less 16 : 9 picture squeezed signal at 2.5 v or more this pin is pulled down to gnd by a 100 k resistor, so the 4 : 3 video signal is selected when open.
6 CXA2069Q pin symbol pin equivalent circuit description no. voltage 7 14 21 28 32 33 34 s-1 s-2 s-3 s-4 adr scl sda v c c v c c v c c 5 0 k 7 1 4 2 8 2 1 1 0 0 k 1 0 0 k 5 0 k 5 v v c c 1 4 7 7 2 k 2 8 k 3 2 v c c 1 0 . 5 k 4 k 3 3 v c c 4 k 3 4 composite video/s selector. the detection results are written to the status register. s signal at 3.5 v or less composite video signal at 3.5 v or more this pin is pulled up to 5 v by a 100 k resistor, so the composite video signal is selected when open. selects the slave address for the i 2 c bus. 90h at 1.5 v or less 92h at 2.5 v or more 90h when open. i 2 c bus signal input v il max=1.5 v v ih min=3.0 v i 2 c bus signal input v il max=1.5 v v ih min=3.0 v v ol max=0.4 v
7 CXA2069Q pin symbol pin equivalent circuit description no. voltage 36 55 46 48 50 dc_out trap1 trap2 mute bias 3.8 v 4.5 v v c c 1 0 0 1 k 4 6 5 5 v c c 1 4 7 7 2 k 2 8 k 4 8 v c c 1 4 7 2 0 k 5 0 v c c 2 0 k v c c outputs the s2-compatible dc superimposed onto the cout3 output. the dc is superimposed by connecting this pin to the cout3 output via a capacitor. control is performed by the i 2 c bus. when 0 v is output, q1 is on and the impedance is 5 k . s2 protocol output impedance of 10 3 k is realized by attaching external resistance of 4.7 k . dc_out (bus) output dc 0 4.5 v 1 0 v 2 1.9 v 3 4.5 v connects trap circuit for subcarrier. audio signal output mute. mute off at 1.5 v or less mute on at 2.5 v or more mute off when open. internal reference bias (v cc /2). connect to gnd via a capacitor. v c c 3 6 q 1 1 k 4 k 2 8 k
8 CXA2069Q electrical characteristics (ta=25 c v cc =9 v) item symbol conditions min. typ. max. unit current consumption i cc no signal, no load 40 55 72 ma video system (measurement circuit ; fig. 1) gain frequency response characteristics frequency response characteristics (y/c mix) input dynamic range cross talk gvv fbwv1 fbwv2 ddv vctv f=100 khz, 0.3 vp-p input f=100 khz, input frequency where output amplitude is ? db with 0.3 vp-p output serving as 0 db f=100 khz, maximum with distortion < 1.0 % f=4.43 mhz, 1 vp-p input 5.9 6.4 6.9 db 15 20 mhz 10 15 mhz 1.4 vp-p ?0 db audio system (measurement circuits ; fig. 2 to fig. 5) gain frequency response characteristics total harmonic distortion input dynamic range cross talk ripple rejection ratio output dc offset residual noise s/n ratio gv a fbw a thd dd a vct a vct a voff vn a s/n f=1 khz, 1 vp-p input, 5.7 k resistor inserted to input f=1 khz, input frequency where output amplitude is ? db with 1 vp-p output serving as 0 db f=1 khz, 2.2 vp-p input, where 400 hz hpf+80 khz lpf are inserted f=1 khz, maximum with distortion < 0.3 % f=1 khz, 1 vp-p input f=100 hz, 0.3 vp-p applied to v cc offset voltage between input and output when 400 hz hpf+30 khz lpf are inserted f=1 khz, 1 vrms input f cl =400 hz, f ch =30khz ? 0 1 db 50 khz 0.03 0.05 % 2.8 3.0 vrms ?0 ?0 db ?5 ?0 db ?0 30 mv 0 20 30 vrms ?00 ?0 db
9 CXA2069Q logic system high level input voltage low level input voltage low level output voltage high level input current low level input current maximum clock frequency minimum waiting time for data change minimum waiting time for data transfer start low level clock pulse width high level clock pulse width minimum waiting time for start preparation minimum data hold time minimum data preparation time rise time fall time minimum waiting time for stop preparation v ih v il v ol i ih i il f scl t buf t hd;sta t low t high t su;sta t hd;dat t su;dat t r t f t su;sto with sda 3 ma current supplied v ih =4.5v v il =0.4v 3.0 5.0 v 0 1.5 v 0 0.4 v 0 10 a 0 10 a 0 100 khz 4.7 s 4.0 s 4.7 s 4.0 s 4.7 s 300 ns 250 ns 1 s 300 ns 4.7 s item symbol conditions min. typ. max. unit
10 CXA2069Q 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 1 a d r r v 5 v 5 l v 5 s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 6 v 6 r v 6 l t v t v r t v c x a 2 0 6 9 q 0 . 1 1 0 1 k 2 2 c o n 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 6 0 0 0 . 4 7 7 5 1 6 0 0 1 6 0 0 0 . 4 7 7 5 1 6 0 0 7 5 6 0 0 6 0 0 7 5 6 3 6 2 6 1 6 0 6 4 5 8 5 7 5 6 5 5 5 9 5 4 5 3 5 2 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 4 2 3 1 5 7 5 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 v m e a s u r e m e n t p o i n t 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 1 7 5 1 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 4 7 7 5 2 1 2 2 2 3 2 4 2 0 2 6 2 7 2 8 2 9 2 5 3 0 3 1 3 2 i n p u t s i g n a l v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 s 2 - 2 c i n 1 b i a s y i n 1 m u t e c o u t 2 t r a p 2 r o u t 2 l o u t 2 v c c v o u t 3 r o u t 3 y o u t 3 l o u t 3 c o u t 3 d c o u t a g n d s d a s c l v / y o u t 2 s i g n a l i s i n p u t f r o m o n e o f t h e f o l l o w i n g p i n s : 1 , 3 , 5 , 8 , 1 0 , 1 2 , 1 5 , 1 7 , 1 9 , 2 2 , 2 4 , 2 6 , 3 0 , 6 0 a n d 6 3 . o u t p u t s i g n a l i s m e a s u r e d f r o m o n e o f t h e f o l l o w i n g p i n s : 3 7 , 3 9 , 4 1 , 4 4 , 4 7 , 5 3 , 5 6 a n d 5 8 . 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 1 a d r r v 5 v 5 l v 5 s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 6 v 6 r v 6 l t v t v r t v c x a 2 0 6 9 q 0 . 1 1 0 1 k 2 2 c o n 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 6 0 0 0 . 4 7 7 5 1 6 0 0 1 6 0 0 0 . 4 7 7 5 1 6 0 0 7 5 6 0 0 6 0 0 7 5 6 3 6 2 6 1 6 0 6 4 5 8 5 7 5 6 5 5 5 9 5 4 5 3 5 2 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 4 2 3 1 5 7 5 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 v m e a s u r e m e n t p o i n t 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 1 7 5 1 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 4 7 7 5 2 1 2 2 2 3 2 4 2 0 2 6 2 7 2 8 2 9 2 5 3 0 3 1 3 2 i n p u t s i g n a l 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k c i n 1 b i a s y i n 1 m u t e c o u t 2 t r a p 2 r o u t 2 l o u t 2 v c c v o u t 3 r o u t 3 y o u t 3 l o u t 3 c o u t 3 d c o u t a g n d s d a s c l v / y o u t 2 v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 s 2 - 2 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k s i g n a l i s i n p u t f r o m o n e o f t h e f o l l o w i n g p i n s : 2 , 4 , 9 , 1 1 , 1 6 , 1 8 , 2 3 , 2 5 , 2 9 , 3 1 , 5 9 , 6 1 , 6 2 a n d 6 4 . o u t p u t s i g n a l i s m e a s u r e d f r o m o n e o f t h e f o l l o w i n g p i n s : 3 8 , 4 0 , 4 3 , 4 5 , 5 2 a n d 5 4 . fig. 1 video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit fig. 2 audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit
11 CXA2069Q 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 1 a d r r v 5 v 5 l v 5 s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 6 v 6 r v 6 l t v t v r t v c x a 2 0 6 9 q 0 . 1 1 0 1 k c o n 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 6 0 0 0 . 4 7 7 5 1 6 0 0 1 6 0 0 0 . 4 7 7 5 1 6 0 0 7 5 6 0 0 6 0 0 7 5 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 4 2 3 1 5 7 5 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k v m e a s u r e m e n t p o i n t 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 1 7 5 1 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 4 7 7 5 1 0 0 h z , 0 . 3 v p - p 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 6 3 6 2 6 1 6 0 6 4 5 8 5 7 5 6 5 5 5 9 5 4 5 3 5 2 2 1 2 2 2 3 2 4 2 0 2 6 2 7 2 8 2 9 2 5 3 0 3 1 3 2 c i n 1 b i a s y i n 1 m u t e c o u t 2 t r a p 2 r o u t 2 l o u t 2 v c c v o u t 3 r o u t 3 y o u t 3 l o u t 3 c o u t 3 d c o u t a g n d s d a s c l v / y o u t 2 v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 s 2 - 2 a f = 1 0 0 h z , 0 . 3 v p - p s i g n a l i s a p p l i e d t o v c c a n d t h e o u t p u t s i g n a l s f r o m p i n s 3 8 , 4 0 , 4 3 , 4 5 , 5 2 a n d 5 4 a r e m e a s u r e d . 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 1 a d r r v 5 v 5 l v 5 s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 6 v 6 r v 6 l t v t v r t v c x a 2 0 6 9 q 0 . 1 1 0 1 k 2 2 c o n 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 6 0 0 0 . 4 7 7 5 1 6 0 0 1 6 0 0 0 . 4 7 7 5 1 6 0 0 7 5 6 0 0 6 0 0 7 5 6 3 6 2 6 1 6 0 6 4 5 8 5 7 5 6 5 5 5 9 5 4 5 3 5 2 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 4 2 3 1 5 7 5 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 v m e a s u r e m e n t p o i n t 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 1 7 5 1 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 4 7 7 5 2 1 2 2 2 3 2 4 2 0 2 6 2 7 2 8 2 9 2 5 3 0 3 1 3 2 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k v m e a s u r e m e n t p o i n t c i n 1 b i a s y i n 1 m u t e c o u t 2 t r a p 2 r o u t 2 l o u t 2 v c c v o u t 3 r o u t 3 y o u t 3 l o u t 3 c o u t 3 d c o u t a g n d s d a s c l v / y o u t 2 v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 v 3 l v 3 y 3 r v 3 c 3 s - 2 s 2 - 2 fig. 3 audio system (ripple rejection ratio) measurement circuit fig. 4 audio system (output dc offset voltage) measurement circuit
12 CXA2069Q 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 1 a d r r v 5 v 5 l v 5 s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 6 v 6 r v 6 l t v t v r t v c x a 2 0 6 9 q 0 . 1 1 0 1 k 2 2 c o n 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 6 0 0 0 . 4 7 7 5 1 6 0 0 1 6 0 0 0 . 4 7 7 5 1 6 0 0 7 5 6 0 0 6 0 0 7 5 6 3 6 2 6 1 6 0 6 4 5 8 5 7 5 6 5 5 5 9 5 4 5 3 5 2 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 7 5 6 0 0 6 0 0 7 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 4 2 3 1 5 7 5 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 v m e a s u r e m e n t p o i n t 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 1 7 5 1 6 0 0 0 . 4 7 7 5 1 6 0 0 0 . 4 7 7 5 2 1 2 2 2 3 2 4 2 0 2 6 2 7 2 8 2 9 2 5 3 0 3 1 3 2 4 0 d b 4 . 5 v c i n 1 b i a s y i n 1 m u t e c o u t 2 t r a p 2 r o u t 2 l o u t 2 v c c v o u t 3 r o u t 3 y o u t 3 l o u t 3 c o u t 3 d c o u t a g n d s d a s c l v / y o u t 2 v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 s 2 - 2 fig. 5 audio system (residual noise) measurement circuit
13 CXA2069Q application circuit 7 5 0 . 4 7 4 7 0 k 1 7 5 0 . 4 7 4 7 0 k 1 0 . 1 1 7 5 7 5 0 . 4 7 4 7 0 k 1 7 5 0 . 4 7 4 7 0 k 1 0 . 1 1 7 5 7 5 0 . 4 7 4 7 0 k 1 7 5 0 . 4 7 4 7 0 k 1 0 . 1 1 7 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 4 2 3 1 5 1 0 . 4 7 1 1 0 . 1 1 0 . 4 7 1 0 . 4 7 7 5 a d r r v 5 v 5 l v 5 s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 6 v 6 r v 6 l t v t v r t v c x a 2 0 6 9 q 1 0 . 4 7 1 0 . 4 7 1 1 1 0 p 1 8 0 6 2 0 2 1 2 2 2 3 2 4 2 0 2 6 2 7 2 8 2 9 2 5 3 0 3 1 3 2 0 . 1 1 0 c o m b f i l t e r 0 . 4 7 1 k 1 0 p 1 8 0 6 2 0 2 2 0 . 1 2 2 0 2 2 0 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 6 3 6 2 6 1 6 0 6 4 5 8 5 7 5 6 5 5 5 9 5 4 5 3 5 2 v i d e o 2 o u t p u t v i d e o 3 o u t p u t v i d e o 1 i n p u t v i d e o 2 i n p u t v i d e o 3 i n p u t v i d e o 1 o u t p u t v i d e o 6 i n p u t t v i n p u t v i d e o 5 i n p u t v i d e o 4 i n p u t c o n c i n 1 b i a s y i n 1 m u t e c o u t 2 t r a p 2 r o u t 2 l o u t 2 v c c v o u t 3 r o u t 3 y o u t 3 l o u t 3 c o u t 3 d c o u t a g n d s d a s c l v / y o u t 2 v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 s 2 - 2 d r i v e t h i s i n p u t w i t h l o w i m p e d a n c e t o p r e v e n t c r o s s t a l k f o r t h i s p i n . d e p e n d i n g o n t h e o u t p u t b i a s o f t h e c o m b f i l t e r s , p a y a t t e n t i o n t o t h e p o l a r i t i e s o f t h e c a p a c i t o r s s i n c e t h e b i a s a t p i n s 4 9 a n d 5 1 i s a p p r o x i m a t e l y 3 . 1 v a n d 4 . 5 v , r e s p e c t i v e l y . c o n n e c t p i n 3 2 t o v c c w h e n s e t t i n g t h e s l a v e a d d r e s s o f t h e i c t o 9 2 h . t h e a u d i o o u t p u t c a n b e m u t e d b y s e t t i n g p i n 4 8 t o 3 . 5 v o r m o r e . t h e t r a p s ( p i n s 4 6 a n d 5 5 ) a r e o f 3 . 5 8 m h z s u b c a r r i e r . t h e o u t p u t i m p e d a n c e o f t h e a u d i o s i g n a l s o u r c e m u s t b e 4 . 7 k w . p a y a t t e n t i o n t o t h e p o l a r i t i e s o f t h e c a p a c i t o r s s i n c e e a c h o u t p u t o f v i d e o s y s t e m a n d a u d i o s y s t e m h a s o p t i o n a l b i a s , r e s p e c t i v e l y . application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
14 CXA2069Q i 2 c bus control signal fig. 6 i 2 c bus control signal timing chart description of operation the CXA2069Q is a tv i 2 c bus-compatible av switch ic. the video system and the stereo audio system both have 7 inputs and 3 outputs each. 4 of the 7 video system inputs support s2 and s protocols. the desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by i 2 c bus control. however, the same input is assigned to both the video and audio system output 3. i 2 c bus registers 1) i 2 c bus the i 2 c bus (inter-ic bus) is an inter-ic bus system developed by philips. two lines (sda?erial data, scl?erial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. the ic outputs are either open collector or open drain, forming a bus line in the wired or format. s : start condition ; sda is set ?ow?when scl is ?igh p : stop condition ; sda is set ?igh?when scl is ?igh a : acknowledge ; signal sent from the slave data is transmitted by msb-first. one data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. normally, the slave * 1 ic receives data at the rising edge of scl and the master * 2 ic changes data at the falling edge of scl. * 1 slave : an ic that is placed under the control of the master. in a normal system, all devices excluding the central microcomputer are slaves. * 2 master : a central microcomputer or other controlling ic. t b u f p s s p t l o w t h d ; s t a t r t h d ; d a t t h i g h t f t s u ; d a t t s u ; s t a t s u ; s t o s d a s c l 3 4 3 3 s d a a a s p m s b l s b m s b l s b 1 2 3 4 5 6 7 8 9 1 2 9 s c l
15 CXA2069Q 2) control registers the CXA2069Q control is exercised by writing 3-byte data into the three 8-bit control registers which control the output selector circuits for the 3 outputs. s ; start condition a ; acknowledge p ; stop condition o control register structure (data1 to data3) all registers are set to ??during ic power on. * ?indicates undefined. s slave address a data1 a data2 a data3 a p b7 b6 b5 b4 b3 b2 b1 b0 slave add. data1 data2 data3 1 0 0 1 0 0 adr r/w a-gain s/comp1 v-in1 a-in1 v/yout s/comp2 v-in2 a-in2 * s/comp3 av-in3 dc out * r/w (1) : read/write mode 0 : control data write 1 : status register read adr (1) : this bit sets the slave address set by the address pin. 0 : 90h 1 : 92h a-gain (1) : lout1/rout1 output gain selector 0 : 0 db output 1 : ? db output s/comp1 to s/comp3 (1 each) : s terminal input/composite signal input selectors by setting s/comp1 to ?? when composite signal input is selected, yout1/cout1 output the inputs from yin1/cin1 during video 1 output. 0 : composite signal inputs (tv, v1 to v6 inputs) 1 : s terminal inputs (y1/c1 to y4/c4 inputs) v/yout (1) : this bit selects the output to pin 44 (v/yout2). 0 : vout (composite signal) output 1 : yout (luminance signal) output v-in1 to v-in2 (3 each) : these bits select the input signals output to each video output. v-in1 corresponds to the vout1 and yout1/cout1 outputs, and v-in2 to the vout2 and yout2/cout2 outputs. 0 : mute 4 : selects the v3 and y3/c3 inputs 1 : selects the tv input 5 : selects the v4 and y4/c4 inputs 2 : selects the v1 and y1/c1 inputs 6 : selects the v5 input 3 : selects the v2 and y2/c2 inputs 7 : selects the v6 input
16 CXA2069Q a-in1 to a-in2 (3 each) : these bits select the input signals output to each audio output. a-in1 corresponds to the lout1/rout1 outputs, and a-in2 to the lout2/rout2 outputs. 0 : mute 4 : selects the lv3/rv3 inputs 1 : selects the ltv/rtv inputs 5 : selects the lv4/rv4 inputs 2 : selects the lv1/rv1 inputs 6 : selects the lv5/rv5 inputs 3 : selects the lv2/rv2 inputs 7 : selects the lv6/rv6 inputs av-in3 (3) : this bit selects the input signals output to output 3. both the video output and the audio output are selected at the same time only for av-in3. 0 : mute 4 : selects the v3, y3/c3 and lv3/rv3 inputs 1 : selects the tv and ltv/rtv inputs 5 : selects the v4, y4/c4 and lv4/rv4 inputs 2 : selects the v1, y1/c1 and lv1/rv1 inputs 6 : selects the v5 and lv5/rv5 inputs 3 : selects the v2, y2/c2 and lv2/rv2 inputs 7 : selects the v6 and lv6/rv6 inputs dc out (2) : these bits set the dc voltage output from pin 35 (dc out). 0 : 4.5 v 1 : 0 v 2 : 1.9 v 3 : 4.5 v 3) status registers when reading two bytes when reading one byte s ; start condition a ; acknowledge na ; no acknowledge p ; stop condition when communication is to be terminated in the status register reading mode, the ?o-acknowledge signal is needed to assure that the master does not issue the acknowledge signal to the slave. it is possible to read only data1 of the status register by sending the no-acknowledge signal after data1. o status register structure (data1 to data2) s slave address a data1 a data2 na p s slave address a data1 na p b7 b6 b5 b4 b3 b2 b1 b0 slave add. data1 data2 1 0 0 1 0 0 adr 1 s1sel s2sel s3sel s4sel s-c1 s-c2 s1sel s2sel s3sel s4sel s-c3 s-c4
17 CXA2069Q s1sel to s4sel (1 each) : s-1 to s-4 pin status 0 ; s-1 to s-4 pins are not grounded. 1 ; s-1 to s-4 pins are grounded. s1sel to s4sel are actually determined by comparing the s-1 to s-4 pin dc voltages with 3.5 v. s-c1, s-c2, s-c3, s-c4 (2 each) : s2-1, s2-2, s2-3 and s2-4 pin status 0 ; 4 : 3 video signal 1 ; 4 : 3 letter-box signal 2 ; 16 : 9 video squeezed signal 3 ; no signal s-c1 to s-c4 are actually determined by comparing the s2-1 to s2-4 pin dc voltages with two threshold. however, when the s-1 to s-4 pins are open, the outputs are fixed to ?? 4) power-on reset the CXA2069Q has an internal power-on reset function that sets each control register to ??during ic power on. the power-on reset v th has hysteresis. s-1 to s-4 pin dc voltage 3.5 v or more 3.5 v or less s1sel to s4sel 0 1 s2-1 to s2-4 pin dc voltage 1.3 v or less 1.3 v or more to 2.5 v or less 2.5 v or more s-1 to s-4 open s-c1 to s-c4 0 1 2 3 4 . 5 v 5 . 6 v v c c p o w e r - o n r e s e t p o w e r - o n r e s e t r e l e a s e d
18 CXA2069Q v i d e o s y s t e m f r e q u e n c y r e s p o n s e c h a r a c t e r i s t i c s f r e q u e n c y [ h z ] v i d e o s y s t e m i n p u t / o u t p u t g a i n [ d b ] 8 6 4 2 2 0 1 m 1 0 m 1 0 0 m a u d i o s y s t e m f r e q u e n c y r e s p o n s e c h a r a c t e r i s t i c s f r e q u e n c y [ h z ] a u d i o s y s t e m i n p u t / o u t p u t g a i n [ d b ] 2 0 2 4 8 6 1 0 k 1 0 0 k 1 m a u d i o s y s t e m d i s t o r t i o n v s . i n p u t a m p l i t u d e i n p u t a m p l i t u d e [ v r m s ] t o t a l h a r m o n i c d i s t o r t i o n [ % ] 1 0 1 0 . 1 0 . 0 1 0 . 0 0 2 1 2 3 4 f = 1 k h z 4 0 0 h z h p f , 8 0 k h z l p f 0 1 0 0 k 1 k y 1 / c 1 t o y 4 / c 4 ? v o u t 1 t o v o u t 3 l / r t v , l / r 1 t o l / r 6 ? l o u t 1 ( 6 d b ) l o u t 2 a n d l o u t 3 o u t p u t s l o u t 1 o u t p u t ( 0 d b g a i n ) t v , v 1 t o v 6 ? v o u t 1 t o v o u t 3 y 1 t o y 4 ? y o u t 1 t o y o u t 3 c 1 t o c 4 ? c o u t 1 t o c o u t 3 l / r t v , l / r 1 t o l / r 6 ? l o u t 1 ( 0 d b ) l / r t v , l / r 1 t o l / r 6 ? l o u t 2 t o l o u t 3
s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 2 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p - 6 4 p - l 0 1 q f p 0 6 4 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g 1 . 0 0 t o 1 0 package outline unit : mm CXA2069Q 19

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